The present invention relates to multi-chip modules and fabricating methods thereof and more particularly, to a multi-chip module and a fabricating method thereof, in which two or more semiconductor chips are integrated in one single package unit for offering manifold increase in functionality or data storage capacity.
Multi-chip module technology allows two or more semiconductor chips to be integrated in one single package unit and then connected to a printed circuit board for forming a multi-chip module, which is capable of offering a manifold level of functionality or data storage capacity. Similarly, a general memory module, such as a flash memory module, typically has two or more memory chips integrated in one single memory module for providing significant increase in data storage capacity.
Illustrated in FIG. 1 and FIG. 2 are two conventional multi-chip modules. Referring to FIG. 1, a conventional multi-chip module is constructed based on a stacked dual-chip BGA (Ball Grid Array) semiconductor package, including (a) a substrate 100; (b) a first semiconductor chip 110 mounted on the substrate 100; (c) a second semiconductor chip 120 stacked on the first semiconductor chip 110; (d) a set of first bonding wires 131 for electrically connecting the first semiconductor chip 110 to the substrate 100; (e) a set of second bonding wires 132 for electrically connecting the second semiconductor chip 120 to the substrate 100; (f) an encapsulant 140 for encapsulating the two semiconductor chips 110, 120; and (g) ball grid array 150 implanted on a back side of the substrate 100 for mechanically bonding and electrically connecting the BGA package to a printed circuit board (PCB) 160. After the BGA package is mounted on the PCB 160, a plurality of passive components 170 are further bonded to predetermined positions on the PCB 160 beside the BGA package. This results in a dual-chip module.
FIG. 2 shows another conventional multi-chip module constructed based on a dual-chip COC (Chip-On-Chip) BGA semiconductor package, including: (a) a substrate 200; (b) a first semiconductor chip 210 mounted on the substrate 200; (c) a second semiconductor chip 220 mounted on the first semiconductor chip 210 through a plurality of solder bumps 221 by using chip-on-chip (COC) technology; (d) a set of bonding wires 230 for electrically connecting the first semiconductor chip 210 to the substrate 200; (e) an encapsulant 240 for encapsulating the two semiconductor chips 210, 220; and (g) ball grid array 250 implanted on a back side of the substrate 200 for mechanically bonding and electrically connecting the semiconductor package to a PCB 260. After the semiconductor package is mounted on the PCB 260, a plurality of passive components 270 are further bonded to predetermined positions on the PCB 260 beside the semiconductor package. This also results in a dual-chip module.
One common drawback to the foregoing two dual-chip modules, however, is that a relatively larger PCB is required for disposing the semiconductor package together with the associated passive components thereon, which undesirably makes the resulted dual-chip modules less compact in size.
Related patents include, for example, U.S. Pat. No. 5,646,828 entitled xe2x80x9cTHIN PACKAGING OF MULTI-CHIP MODULES WITH ENHANCED THERMAL/POWER MANAGEMENTxe2x80x9d; U.S. Pat. No. 5,477,082 entitled xe2x80x9cBI-PLANAR MULTI-CHIP MODULExe2x80x9d; and U.S. Pat. No. 5,784,261 entitled xe2x80x9cMICROCHIP MODULE ASSEMBLIESxe2x80x9d; to name just a few.
The above patents, however, still have the foregoing drawback of making the resulted multi-chip module less compact in size. Therefore, it is desired to construct a multi-chip module more miniaturized in profile.
A primary objective of the present invention is to provide multi-chip module and a fabricating method thereof, in which the multi-chip module can be made more compact in size while allowing high density of integration.
In accordance with the foregoing and other objectives, the invention proposes a new multi-chip module and a fabricating method thereof.
The fabricating method of the invention is firstly to prepare a first semiconductor chip and at least one second semiconductor chip; wherein the first semiconductor chip is larger in area size than the second semiconductor chip and is partitioned at least into a first connecting region and a second connecting region. The multi-chip module constructed according to the invention can contain two, three, four or more chips, depending on the area size of the first semiconductor chip.
With the use of chip-on-chip (COC) technology, the second chip is mounted on the second connecting region of the first semiconductor chip. Subsequently, the first connecting region of the first semiconductor chip is disposed on an upper surface of a substrate by using flip-chip technology. Then, the substrate has a lower surface attached to a printed circuit board through surface-mount technology (SMT). Moreover, at least one passive component is bonded to the printed circuit board (PCB) at a predetermined position beside the substrate and directly beneath the second semiconductor chip. This arrangement allows a PCB having a smaller layout area to be used in the invention, making the resulted multi-chip module more compact in size than the prior art.